NXP Semiconductors LPC24XX UM10237 - Manual (Page 671)

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User manual Rev. 04 — 26 August 2009 671 of 792
NXP Semiconductors
UM10237
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
5.3 A/D Status Register (AD0STAT - 0xE003 4030)
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
Table 594: A/D Global Data Register (AD0GDR - address 0xE003 4004) bit description
Bit Symbol Description Reset
Value
5:0 Unused These bits always read as zeroes. They provide compatible expansion
room for future, higher-resolution A/D converters. 0
15:6 V/V
REF
When DONE is 1, this field contains a binary fraction representing the
voltage on the Ain pin selected by the SEL field, divided by the voltage
on the V
DDA
pin. Zero in the field indicates that the voltage on the Ain
pin was less than, equal to, or close to that on V
SSA
, while 0x3FF
indicates that the voltage on Ain was close to, equal to, or greater than
that on V
REF
.
X
23:16 Unused These bits always read as zeroes. They allow accumulation of
successive A/D values without AND-masking, for at least 256 values
without overflow into the CHN field. 0
26:24 CHN These bits contain the channel from which the LS bits were converted. X
29:27 Unused These bits always read as zeroes. They could be used for expansion of
the CHN field in future compatible A/D converters that can convert more
channels. 0
30 OVERU
N This bit is 1 in burst mode if the results of one or more conversions was
(were) lost and overwritten before the conversion that produced the
result in the LS bits. In non-FIFO operation, this bit is cleared by reading
this register. 0
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared
when this register is read and when the ADCR is written. If the ADCR is
written while a conversion is still in progress, this bit is set and a new
conversion is started. 0
Table 595: A/D Status Register (AD0STAT - address 0xE003 4030) bit description
Bit Symbol Description Reset
Value
7:0 Done7:0 These bits mirror the DONE status flags that appear in the result
register for each A/D channel. 0
15:8 Overrun7:0 These bits mirror the OVERRRUN status flags that appear in the
result register for each A/D channel. Reading ADSTAT allows
checking the status of all A/D channels simultaneously.
0
16 ADINT This bit is the A/D interrupt flag. It is one when any of the individual
A/D channel Done flags is asserted and enabled to contribute to the
A/D interrupt via the ADINTEN register. 0
31:17 Unused Unused, always 0. 0