NXP Semiconductors LPC24XX UM10237 - Manual (Page 56)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 56 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
M = (F
CCO
× N) / (2 × F
IN
)
The smallest frequency for F
CCO
that can produce our desired CPU clock rate and is
within the PLL operating range is 288 MHz (4
× 72 MHz). Start by assuming N = 1, since
this produces the smallest multiplier needed for the PLL.
So, M = 288
Ч 10 6 / (2
Ч 32,768) = 4,394.53125. This is not an integer, so the CPU
frequency will not be exactly 288 MHz with this setting. Since this case is less obvious, it
may be useful to make a table of possibilities for different values of N (see
Table 4–52 ).
Beyond N = 7, the value of M is out of range or not supported, so the table stops there. In
the table, the calculated M value is rounded to the nearest integer. If this results in CCLK
being above the maximum operating frequency (72 MHz), it is allowed if it is not more than
1/2
% above the maximum frequency.
In general, larger vlaues of F
REF
result in a more stable PLL when the input clock is a low
frequency. Even the first table entry shows a very small error of just over 1 hundredth of a
percent, or 107 parts per million (ppm). If that is not accurate enough in the application,
the second case gives a much smaller error of 7 ppm.
Remember that when a frequency below about 1 MHz is used as the PLL clock source,
not all multiplier values are available. As it turns out, all of the rounded M values found in
Table 4–52 of this exmaple are supported, as may be confirmed in Table 4–51 .
If PLL calculations suggest use of unsupported multiplier values, those values must be
disregarded and other values examined to find the best fit. Multiplier values one count off
from calculated values may also be good possibilities..
The value written to PLLCFG for the second table entry would be 0x12254
(N - 1 = 1 = 0x1; M - 1 = 8788 = 0x2254).
3.2.14 PLL setup sequence
The following sequence must be followed step by step in order to have the PLL initialized
an running:
1. Disconnect the PLL with one feed sequence if PLL is already connected.
2. Disable the PLL with one feed sequence.
3. Change the CPU Clock Divider setting to speed up operation without the PLL, if
desired.
4. Write to the Clock Source Selection Control register to change the clock source.
5. Write to the PLLCFG and make it effective with one feed sequence. The PLLCFG can
only be updated when the PLL is disabled.
Table 52. Potential values for PLL example
N M M Rounded F
REF
(Hz) F
CCO
(MHz) Actual
CCLK (MHz)
% Error
1 4394.53125 4395 32768 288.0307 72.0077 0.0107
2 8789.0625 8789 16384 287.9980 71.9995 -0.0007
3 13183.59375 13184 10922.67 288.0089 72.0022 0.0031
4 17578.125 17578 8192 287.9980 71.9995 -0.0007
5 21972.65625 21973 6553.6 288.0045 72.0011 0.0016