9 status decoder and status register, Register description, Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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User manual
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NXP Semiconductors
UM10237
Chapter 22: LPC24XX I
2
C interfaces I
2
C0/1/2
The contents of the I
2
C control register may be read as I2CONSET. Writing to I2CONSET
will set bits in the I
2
C control register that correspond to ones in the value written.
Conversely, writing to I2CONCLR will clear bits in the I
2
C control register that correspond
to ones in the value written.
7.9 Status decoder and status register
The status decoder takes all of the internal status bits and compresses them into a 5 bit
code. This code is unique for each I
2
C bus status. The 5 bit code may be used to generate
vector addresses for fast processing of the various service routines. Each service routine
processes a particular bus status. There are 26 possible bus states if all four modes of the
I
2
C block are used. The 5 bit status code is latched into the five most significant bits of the
status register when the serial interrupt flag is set (by hardware) and remains stable until
the interrupt flag is cleared by software. The three least significant bits of the status
register are always zero. If the status code is used as a vector to service routines, then the
routines are displaced by eight address locations. Eight bytes of code is sufficient for most
of the service routines (see the software example in this section).
8.
Register description
Each I
2
C interface contains 7 registers as shown in
below.
Table 512. Summary of I
2
C registers
Generic
Name
Description
Access
Reset
value
I
2
Cn Register
Name & Address
I2CONSET I2C Control Set Register. When a one is written to a
bit of this register, the corresponding bit in the I
2
C
control register is set. Writing a zero has no effect on
the corresponding bit in the I
2
C control register.
R/W
0x00
I2C0CONSET - 0xE001 C000
I2C1CONSET - 0xE005 C000
I2C2CONSET - 0xE008 0000
I2STAT
I2C Status Register.
During I
2
C operation, this
register provides detailed status codes that allow
software to determine the next action needed.
RO
0xF8
I2C0STAT - 0xE001 C004
I2C1STAT - 0xE005 C004
I2C2STAT - 0xE008 0004
I2DAT
I2C Data Register.
During master or slave transmit
mode, data to be transmitted is written to this register.
During master or slave receive mode, data that has
been received may be read from this register.
R/W
0x00
I2C0DAT - 0xE001 C008
I2C1DAT - 0xE005 C008
I2C2DAT - 0xE008 0008
I2ADR
I2C Slave Address Register.
Contains the 7 bit slave
address for operation of the I
2
C interface in slave
mode, and is not used in master mode. The least
significant bit determines whether a slave responds to
the general call address.
R/W
0x00
I2C0ADR - 0xE001 C00C
I2C1ADR - 0xE005 C00C
I2C2ADR - 0xE008 000C