NXP Semiconductors LPC24XX UM10237 - Manual (Page 574)

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User manual Rev. 04 — 26 August 2009 574 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
5. Pin description
6. I 2 C operating modes
In a given application, the I 2 C block may operate as a master, a slave, or both. In the slave
mode, the I 2 C hardware looks for its own slave address and the general call address. If
one of these addresses is detected, an interrupt is requested. If the processor wishes to
become the bus master, the hardware waits until the bus is free before the master mode is
entered so that a possible slave operation is not interrupted. If bus arbitration is lost in the
master mode, the I
2 C block switches to the slave mode immediately and can detect its
own slave address in the same serial transfer.
6.1 Master Transmitter mode
In this mode data is transmitted from master to slave. Before the master transmitter mode
can be entered, the I2CONSET register must be initialized as shown in
Table 22–510 .
I2EN must be set to 1 to enable the I 2 C function. If the AA bit is 0, the I 2 C interface will not
acknowledge any address when another device is master of the bus, so it can not enter
slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the
SIC bit in the I2CONCLR register.
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this mode the data direction bit (R/W) should be 0 which means
Write. The first byte transmitted contains the slave address and Write bit. Data is
transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received.
START and STOP conditions are output to indicate the beginning and the end of a serial
transfer.
The I 2 C interface will enter master transmitter mode when software sets the STA bit. The
I 2 C logic will send the START condition as soon as the bus is free. After the START
condition is transmitted, the SI bit is set, and the status code in the I2STAT register is
0x08. This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit. SI is cleared by
writing a 1 to the SIC bit in the I2CONCLR register. The STA bit should be cleared after
writing the slave address.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes now are 0x18,
0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xB0 if the slave mode was enabled
(by setting AA to 1). The appropriate actions to be taken for each of these status codes
are shown in
Table 22–525 to Table 22–528 .
Table 509. I 2 C Pin Description
Pin Type Description
SDA0,1, 2 Input/Output I 2 C Serial Data
SCL0,1, 2 Input/Output I 2 C Serial Clock
Table 510. I2CnCONSET used to configure Master mode
Bit 7 6 5 4 3 2 1 0
Symbol - I2EN STA STO SI AA - -
Value - 1 0 0 0 0 - -