Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual

Page 774

UM10237_4

User manual

Rev. 04 — 26 August 2009

774 of 792

NXP Semiconductors

UM10237

Chapter 36: LPC24XX Supplementary information

Fig 88. Message overwritten indicated by semaphore bits

and message lost. . . . . . . . . . . . . . . . . . . . . . . .516

Fig 89. Message overwritten indicated by message lost517
Fig 90. Clearing message lost . . . . . . . . . . . . . . . . . . . .518
Fig 91. Detailed example of acceptance filter tables and ID

index values . . . . . . . . . . . . . . . . . . . . . . . . . . . .520

Fig 92. ID Look-up table configuration example (no

FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .522

Fig 93. ID Look-up table configuration example (FullCAN

activated and enabled) . . . . . . . . . . . . . . . . . . .524

Fig 94. SPI data transfer format (CPHA = 0 and

CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527

Fig 95. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .535
Fig 96. Texas Instruments Synchronous Serial Frame

Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .538

Fig 97. SPI frame format with CPOL=0 and CPHA=0 (a)

Single and b) Continuous Transfer) . . . . . . . . . .539

Fig 98. SPI frame format with CPOL=0 and CPHA=1 . .540
Fig 99. SPI frame format with CPOL = 1 and CPHA = 0 (a)

Single and b) Continuous Transfer) . . . . . . . . . .541

Fig 100. SPI Frame Format with CPOL = 1 and

CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542

Fig 101. Microwire frame format (single transfer) . . . . . .543
Fig 102. Microwire frame format (continuos transfers) . .544
Fig 103. Microwire frame format setup and hold details .544
Fig 104. Multimedia card system . . . . . . . . . . . . . . . . . . .552
Fig 105. Secure digital memory card connection. . . . . . .553
Fig 106. MCI adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
Fig 107. Command path state machine . . . . . . . . . . . . . .555
Fig 108. MCI command transfer . . . . . . . . . . . . . . . . . . .555
Fig 109. Data path state machine . . . . . . . . . . . . . . . . . .558
Fig 110. Pending command start . . . . . . . . . . . . . . . . . . .560
Fig 111. I

C bus configuration . . . . . . . . . . . . . . . . . . . . .573

Fig 112. Format in the Master Transmitter mode. . . . . . .575
Fig 113. Format of Master Receive mode . . . . . . . . . . . .575
Fig 114. A master receiver switch to master Transmitter after

sending repeated START. . . . . . . . . . . . . . . . . .576

Fig 115. Format of Slave Receiver mode . . . . . . . . . . . .576
Fig 116. Format of Slave Transmitter mode . . . . . . . . . .577
Fig 117. I

C Bus serial interface block diagram. . . . . . . .578

Fig 118. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .579
Fig 119. Serial clock synchronization. . . . . . . . . . . . . . . .580
Fig 120. Format and States in the Master Transmitter

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .590

Fig 121. Format and States in the Master Receiver

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .591

Fig 122. Format and States in the Slave Receiver mode.592
Fig 123. Format and States in the Slave Transmitter

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593

Fig 124. Simultaneous repeated START conditions from 2

masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601

Fig 125. Forced access to a busy I

C bus . . . . . . . . . . . .602

Fig 126. Recovering from a bus obstruction caused by a low

level on SDA . . . . . . . . . . . . . . . . . . . . . . . . . . .602

Fig 127. Simple I2S configurations and bus timing . . . . .613
Fig 128. FIFO contents for various I

S modes. . . . . . . . .620

Fig 129. A timer cycle in which PR=2, MRx=6, and both

interrupt and reset on match are enabled. . . . . 630

Fig 130. A timer Cycle in Which PR=2, MRx=6, and both

interrupt and stop on match are enabled . . . . . 630

LPC2400 parts . . . . . . . . . . . . . . . . . . . . . . . . . 698

Fig 142. Boot process flowchart . . . . . . . . . . . . . . . . . . . 700
Fig 143. IAP parameter passing . . . . . . . . . . . . . . . . . . . 708
Fig 144. GPDMA block diagram . . . . . . . . . . . . . . . . . . . 713
Fig 145. GPDMA in the LPC24XX . . . . . . . . . . . . . . . . . 714
Fig 146. LLI example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Fig 147. EmbeddedICE debug environment block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

Fig 148. ETM debug environment block diagram . . . . . . 747
Fig 149. RealMonitor components . . . . . . . . . . . . . . . . . 749
Fig 150. RealMonitor as a State Machine . . . . . . . . . . . . 750
Fig 151. Exception handlers. . . . . . . . . . . . . . . . . . . . . . 753