NXP Semiconductors LPC24XX UM10237 - Manual (Page 779)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 779 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
7.1.3 Back-to-Back Inter-Packet-Gap Register (IPGT -
0xFFE0 0008) . . . . . . . . . . . . . . . . . . . . . . . . 223
7.1.4 Non Back-to-Back Inter-Packet-Gap Register
(IPGR - 0xFFE0 000C) . . . . . . . . . . . . . . . . . 223
7.1.5 Collision Window / Retry Register (CLRT -
0xFFE0 0010) . . . . . . . . . . . . . . . . . . . . . . . . 223
7.1.6 Maximum Frame Register (MAXF -
0xFFE0 0014) . . . . . . . . . . . . . . . . . . . . . . . . 224
7.1.7 PHY Support Register (SUPP -
0xFFE0 0018) . . . . . . . . . . . . . . . . . . . . . . . . 224
7.1.8 Test Register (TEST - 0xFFE0 001C). . . . . . 224
7.1.9 MII Mgmt Configuration Register (MCFG -
0xFFE0 0020) . . . . . . . . . . . . . . . . . . . . . . . . 225
7.1.10 MII Mgmt Command Register (MCMD -
0xFFE0 0024) . . . . . . . . . . . . . . . . . . . . . . . . 225
7.1.11 MII Mgmt Address Register (MADR -
0xFFE0 0028) . . . . . . . . . . . . . . . . . . . . . . . . 226
7.1.12 MII Mgmt Write Data Register (MWTD -
0xFFE0 002C) . . . . . . . . . . . . . . . . . . . . . . . 226
7.1.13 MII Mgmt Read Data Register (MRDD -
0xFFE0 0030) . . . . . . . . . . . . . . . . . . . . . . . . 226
7.1.14 MII Mgmt Indicators Register (MIND -
0xFFE0 0034) . . . . . . . . . . . . . . . . . . . . . . . . 226
7.1.15 Station Address 0 Register (SA0 -
0xFFE0 0040) . . . . . . . . . . . . . . . . . . . . . . . . 227
7.1.16 Station Address 1 Register (SA1 -
0xFFE0 0044) . . . . . . . . . . . . . . . . . . . . . . . . 227
7.1.17 Station Address 2 Register (SA2 -
0xFFE0 0048) . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2 Control register definitions . . . . . . . . . . . . . . 228
7.2.1 Command Register (Command -
0xFFE0 0100) . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2.2 Status Register (Status - 0xFFE0 0104) . . . . 229
7.2.3 Receive Descriptor Base Address Register
(RxDescriptor - 0xFFE0 0108) . . . . . . . . . . . 229
7.2.4 Receive Status Base Address Register (RxStatus
- 0xFFE0 010C) . . . . . . . . . . . . . . . . . . . . . . 230
7.2.5 Receive Number of Descriptors Register
(RxDescriptor - 0xFFE0 0110) . . . . . . . . . . . 230
7.2.6 Receive Produce Index Register
(RxProduceIndex - 0xFFE0 0114) . . . . . . . . 230
7.2.7 Receive Consume Index Register
(RxConsumeIndex - 0xFFE0 0118) . . . . . . . 231
7.2.8 Transmit Descriptor Base Address Register
(TxDescriptor - 0xFFE0 011C) . . . . . . . . . . . 231
7.2.9 Transmit Status Base Address Register (TxStatus
- 0xFFE0 0120). . . . . . . . . . . . . . . . . . . . . . . 231
7.2.10 Transmit Number of Descriptors Register
(TxDescriptorNumber - 0xFFE0 0124) . . . . . 232
7.2.11 Transmit Produce Index Register
(TxProduceIndex - 0xFFE0 0128) . . . . . . . . 232
7.2.12 Transmit Consume Index Register
(TxConsumeIndex - 0xFFE0 012C) . . . . . . . 233
7.2.13 Transmit Status Vector 0 Register (TSV0 -
0xFFE0 0158) . . . . . . . . . . . . . . . . . . . . . . . . 233
7.2.14 Transmit Status Vector 1 Register (TSV1 -
0xFFE0 015C) . . . . . . . . . . . . . . . . . . . . . . . 234
7.2.15 Receive Status Vector Register (RSV -
0xFFE0 0160) . . . . . . . . . . . . . . . . . . . . . . . 234
7.2.16 Flow Control Counter Register
(FlowControlCounter - 0xFFE0 0170) . . . . . 235
7.2.17 Flow Control Status Register (FlowControlStatus -
0xFFE0 0174) . . . . . . . . . . . . . . . . . . . . . . . 236
7.3 Receive filter register definitions . . . . . . . . . 236
7.3.1 Receive Filter Control Register (RxFilterCtrl -
0xFFE0 0200) . . . . . . . . . . . . . . . . . . . . . . . 236
7.3.2 Receive Filter WoL Status Register
(RxFilterWoLStatus - 0xFFE0 0204) . . . . . . 237
7.3.3 Receive Filter WoL Clear Register
(RxFilterWoLClear - 0xFFE0 0208) . . . . . . . 237
7.3.4 Hash Filter Table LSBs Register (HashFilterL -
0xFFE0 0210) . . . . . . . . . . . . . . . . . . . . . . . 238
7.3.5 Hash Filter Table MSBs Register (HashFilterH -
0xFFE0 0214) . . . . . . . . . . . . . . . . . . . . . . . 238
7.4 Module control register definitions . . . . . . . . 238
7.4.1 Interrupt Status Register (IntStatus -
0xFFE0 0FE0) . . . . . . . . . . . . . . . . . . . . . . . 238
7.4.2 Interrupt Enable Register (IntEnable -
0xFFE0 0FE4) . . . . . . . . . . . . . . . . . . . . . . . 239
7.4.3 Interrupt Clear Register (IntClear -
0xFFE0 0FE8) . . . . . . . . . . . . . . . . . . . . . . . 240
7.4.4 Interrupt Set Register (IntSet -
0xFFE0 0FEC) . . . . . . . . . . . . . . . . . . . . . . . 240
7.4.5 Power-Down Register (PowerDown -
0xFFE0 0FF4) . . . . . . . . . . . . . . . . . . . . . . . 241
8 Descriptor and status formats . . . . . . . . . . . 241
8.1 Receive descriptors and statuses . . . . . . . . 241
8.2 Transmit descriptors and statuses . . . . . . . . 245
9 Ethernet block functional description. . . . . 247
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
9.2 AHB interface. . . . . . . . . . . . . . . . . . . . . . . . 248
9.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
9.4 Direct Memory Access (DMA) . . . . . . . . . . . 248
9.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 251
9.6 Transmit process . . . . . . . . . . . . . . . . . . . . . 252
9.7 Receive process . . . . . . . . . . . . . . . . . . . . . 258
9.8 Transmission retry . . . . . . . . . . . . . . . . . . . . 264
9.9 Status hash CRC calculations . . . . . . . . . . . 264
9.10 Duplex modes . . . . . . . . . . . . . . . . . . . . . . . 265
9.11 IEE 802.3/Clause 31 flow control. . . . . . . . . 265
9.12 Half-Duplex mode backpressure . . . . . . . . . 267
9.13 Receive filtering . . . . . . . . . . . . . . . . . . . . . . 268
9.14 Power management. . . . . . . . . . . . . . . . . . . 270
9.15 Wake-up on LAN . . . . . . . . . . . . . . . . . . . . . 271
9.16 Enabling and disabling receive and transmit 272
9.17 Transmission padding and CRC . . . . . . . . . 274
9.18 Huge frames and frame length checking . . . 275
9.19 Statistics counters . . . . . . . . . . . . . . . . . . . . 275
9.20 MAC status vectors . . . . . . . . . . . . . . . . . . . 275
9.21 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
9.22 Ethernet errors . . . . . . . . . . . . . . . . . . . . . . . 277
9.23 AHB bandwidth . . . . . . . . . . . . . . . . . . . . . . 277
9.23.1 DMA access. . . . . . . . . . . . . . . . . . . . . . . . . 277
9.23.2 Types of CPU access. . . . . . . . . . . . . . . . . . 279
9.23.3 Overall bandwidth . . . . . . . . . . . . . . . . . . . . 279