NXP Semiconductors LPC24XX UM10237 - Manual (Page 69)

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User manual Rev. 04 — 26 August 2009 69 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
3. Pins: Select data, address, and control pins and their modes in PINSEL6/8/9 and
PINMODE6/8/9 (see Section 9–5 ).
4. Configuration: see Table 5–68 to Table 5–71 .
3. Introduction
The LPC2400 External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort
Memory Controller peripheral offering support for asynchronous static memory devices
such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate
SDRAM. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
4. Features
• Dynamic memory interface support including Single Data Rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and Flash, with or
without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8 bit, 16 bit, and 32 bit wide static memory support.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
– Asynchronous page mode read
– Programmable wait states
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts.
That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per
device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
5. EMC functional description
Figure 5–15 shows a block diagram of the EMC.