NXP Semiconductors LPC24XX UM10237 - Manual (Page 104)

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User manual Rev. 04 — 26 August 2009 104 of 792
NXP Semiconductors
UM10237
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see
Table note 6–2 ). This means
that all branches cause memory fetches. All data operations cause a Flash read
because buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
[1] Instruction prefetch is enabled in modes 1 and 2.
[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
6. MAM configuration
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
Table 96. MAM responses to program accesses of various types
Program Memory Request Type MAM Mode
0 1 2
Sequential access, data in latches Initiate Fetch [2] Use Latched
Data
[1]
Use Latched
Data
[1]
Sequential access, data not in latches Initiate Fetch Initiate Fetch [1] Initiate Fetch [1]
Non-sequential access, data in latches Initiate Fetch [2] Initiate Fetch [1][2] Use Latched
Data
[1]
Non-sequential access, data not in
latches Initiate Fetch Initiate Fetch [1] Initiate Fetch [1]
Table 97. MAM responses to data and DMA accesses of various types
Data Memory Request Type MAM Mode
0 1 2
Sequential access, data in latches Initiate Fetch [1] Initiate Fetch [1] Use Latched
Data
Sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch
Non-sequential access, data in latches Initiate Fetch [1] Initiate Fetch [1] Use Latched
Data
Non-sequential access, data not in latches Initiate Fetch Initiate Fetch Initiate Fetch