NXP Semiconductors LPC24XX UM10237 - Manual (Page 49)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 49 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see
Section 4–3.2.9 “PLL Feed register (PLLFEED -
0xE01F C08C)” ).
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
3.2.5 PLL Configuration register (PLLCFG - 0xE01F C084)
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 4–3.2.9 “PLL Feed register (PLLFEED - 0xE01F C08C)” ). Calculations for the
PLL frequency, and multiplier and divider values are found in the Section 4–3.2.11 “PLL
frequency calculation” .
Table 44. PLL Control register (PLLCON - address 0xE01F C080) bit description
Bit Symbol Description Reset
value
0 PLLE PLL Enable. When one, and after a valid PLL feed, this bit will
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register,
Table 4–47 .
0
1 PLLC PLL Connect. Having both PLLC and PLLE set to one followed by a
valid PLL feed sequence, the PLL becomes the clock source for the
CPU, as well as the USB subsystem and. Otherwise, the clock
selected by the Clock Source Selection Multiplexer is used directly
by the LPC2400. See PLLSTAT register,
Table 4–47 .
0
7:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
Table 45. PLL Configuration register (PLLCFG - address 0xE01F C084) bit description
Bit Symbol Description Reset
value
14:0 MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in
Table 4–46 .
Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL see
Section 4–3.2.11 “PLL frequency calculation” .
0
15 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
23:16 NSEL PLL Pre-Divider value. Supplies the value "N" in the PLL frequency
calculations. PLL Pre-Divider value. Supplies the value "N" in the PLL
frequency calculations. Supported values for N are 1 through 32.
Note: For details on selecting the right value for NSEL see Section
4–3.2.11 “PLL frequency calculation” .
0
31:24 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA