NXP Semiconductors LPC24XX UM10237 - Manual (Page 773)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 773 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
4. Figures
Fig 1. LPC2458 block diagram . . . . . . . . . . . . . . . . . . . 11
Fig 2. LPC2460 block diagram . . . . . . . . . . . . . . . . . . .12
Fig 3. LPC2468 block diagram . . . . . . . . . . . . . . . . . . .13
Fig 4. LPC2470 block diagram . . . . . . . . . . . . . . . . . . .14
Fig 5. LPC2478 block diagram . . . . . . . . . . . . . . . . . . .15
Fig 6. LPC2400 system memory map . . . . . . . . . . . . . .18
Fig 7. Peripheral memory map. . . . . . . . . . . . . . . . . . . .19
Fig 8. AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .20
Fig 9. Map of lower memory is showing re-mapped and
re-mappable areas for a LPC2400 part with flash25
Fig 10. Reset block diagram including the wakeup timer.32
Fig 11. Example of start-up after reset. . . . . . . . . . . . . . .33
Fig 12. Clock generation for the LPC2400. . . . . . . . . . . .42
Fig 13. Oscillator modes and models: a) slave mode of
operation, b) oscillation mode of operation, c)
external crystal model used for C
X1
/
X2
evaluation44
Fig 14. PLL block diagram (N = 16, M = 125, USBSEL = 6,
CCLKSEL = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Fig 15. EMC block diagram . . . . . . . . . . . . . . . . . . . . . . .70
Fig 16. 32 bit bank external memory interfaces ( bits
MW = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Fig 17. 16 bit bank external memory interfaces (bits
MW = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Fig 18. 8 bit bank external memory interface
(bits MW = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Fig 19. Typical memory configuration diagram . . . . . . .100
Fig 20. Simplified block diagram of the Memory Accelerator
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Fig 21. Block diagram of the Memory Accelerator
Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Fig 22. Block diagram of the Vectored Interrupt
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Fig 23. LPC2458 pinning TFBGA180 package . . . . . . .120
Fig 24. LPC2400 pinning LQFP208 package . . . . . . . .121
Fig 25. LPC2400 pinning TFBGA208 package . . . . . . .121
Fig 26. Ethernet block diagram . . . . . . . . . . . . . . . . . . .213
Fig 27. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .217
Fig 28. Receive descriptor memory layout. . . . . . . . . . .242
Fig 29. Transmit descriptor memory layout . . . . . . . . . .245
Fig 30. Transmit example memory and registers. . . . . .256
Fig 31. Receive Example Memory and Registers . . . . .262
Fig 32. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .267
Fig 33. Receive filter block diagram. . . . . . . . . . . . . . . .269
Fig 34. Receive Active/Inactive state machine . . . . . . .273
Fig 35. Transmit Active/Inactive state machine . . . . . . .274
Fig 36. LCD controller block diagram. . . . . . . . . . . . . . .287
Fig 37. Cursor movement . . . . . . . . . . . . . . . . . . . . . . .295
Fig 38. Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . .296
Fig 39. Cursor image format . . . . . . . . . . . . . . . . . . . . .297
Fig 40. Power-up and power-down sequences . . . . . . .303
Fig 41. Horizontal timing for STN displays. . . . . . . . . . .323
Fig 42. Vertical timing for STN displays . . . . . . . . . . . . .324
Fig 43. Horizontol timing for TFT displays . . . . . . . . . . .324
Fig 44. Vertical timing for TFT displays . . . . . . . . . . . . .325
Fig 45. USB device controller block diagram . . . . . . . . .332
Fig 46. USB MaxPacketSize register array indexing . . .350
Fig 47. Interrupt event handling . . . . . . . . . . . . . . . . . . 362
Fig 48. UDCA Head register and DMA Descriptors . . . 375
Fig 49. Isochronous OUT endpoint operation example. 383
Fig 50. Data transfer in ATLE mode . . . . . . . . . . . . . . . 384
Fig 51. USB Host controller block diagram . . . . . . . . . . 390
Fig 52. USB OTG controller block diagram. . . . . . . . . . 395
Fig 53. USB OTG port configuration: port U1 OTG
Dual-Role device, port U2 host . . . . . . . . . . . . . 397
Fig 54. USB OTG port configuration: VP_VM mode . . . 398
Fig 55. USB OTG port configuration: port U2 host, port U1
host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Fig 56. USB OTG port configuration: port U1 host, port U2
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Fig 57. Port selection for PORT_FUNC bit 0 = 0 and
PORT_FUNC bit 1 = 0. . . . . . . . . . . . . . . . . . . . 404
Fig 58. USB OTG interrupt handling . . . . . . . . . . . . . . . 410
Fig 59. USB OTG controller with software stack . . . . . . 412
Fig 60. Hardware support for B-device switching from
peripheral state to host state . . . . . . . . . . . . . . 413
Fig 61. State transitions implemented in software during
B-device switching from peripheral to host . . . . 414
Fig 62. Hardware support for A-device switching from host
state to peripheral state. . . . . . . . . . . . . . . . . . . 416
Fig 63. State transitions implemented in software during
A-device switching from host to peripheral . . . . 417
Fig 64. Clocking and power control. . . . . . . . . . . . . . . . 420
Fig 65. Autobaud a) mode 0 and b) mode 1 waveform 436
Fig 66. Algorithm for setting UART dividers . . . . . . . . . 439
Fig 67. UART0, 2 and 3 block diagram . . . . . . . . . . . . . 442
Fig 68. Auto-RTS Functional Timing . . . . . . . . . . . . . . . 454
Fig 69. Auto-CTS Functional Timing . . . . . . . . . . . . . . . 455
Fig 70. Auto-baud a) mode 0 and b) mode 1 waveform 461
Fig 71. Algorithm for setting UART dividers . . . . . . . . . 463
Fig 72. UART1 block diagram . . . . . . . . . . . . . . . . . . . . 466
Fig 73. CAN controller block diagram . . . . . . . . . . . . . . 469
Fig 74. Transmit buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . 470
Fig 75. Receive buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . 471
Fig 76. Global Self-Test (high-speed CAN Bus
example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Fig 77. Local self test (high-speed CAN Bus example). 472
Fig 78. Entry in FullCAN and individual standard identifier
tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Fig 79. Entry in standard identifier range table . . . . . . . 499
Fig 80. Entry in either extended identifier table . . . . . . . 499
Fig 81. ID Look-up table example explaining the search
algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Fig 82. Semaphore procedure for reading an auto-stored
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Fig 83. FullCAN section example of the ID
look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Fig 84. FullCAN message object layout . . . . . . . . . . . . 512
Fig 85. Normal case, no messages lost . . . . . . . . . . . . 514
Fig 86. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Fig 87. Message gets overwritten . . . . . . . . . . . . . . . . . 515