NXP Semiconductors LPC24XX UM10237 - Manual (Page 276)

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User manual Rev. 04 — 26 August 2009 276 of 792
NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
9.21 Reset
The Ethernet block has a hard reset input which is connected to the chip reset, as well as
several soft resets which can be activated by setting the appropriate bit(s) in registers. All
registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise
specified.
Hard reset
After a hard reset, all registers will be set to their default value.
Soft reset
Parts of the Ethernet block can be soft reset by setting bits in the Command register and
the MAC1 configuration register.The MAC1 register has six different reset bits:
• SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the
MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a
hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware
reset.
• SIMULATION RESET: Resets the random number generator in the Transmit Function.
The value after a hardware reset assertion is 0.
• RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the receive function in the MAC. The value after a hardware reset assertion
is 0.
• RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a
hardware reset assertion is 0.
• RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the transmit function in the MAC. The value after a hardware reset
assertion is 0.
• RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after
a hardware reset assertion is 0.
The above reset bits must be cleared by software.
The Command register has three different reset bits:
• TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit datapath, excluding the
MAC portions, including all (read-only) registers in the transmit datapath, as well as
the TxProduceIndex register in the host registers module. A soft reset of the transmit
datapath will abort all AHB transactions of the transmit datapath. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Tx datapath will clear
the TxStatus bit in the Status register.
• RxReset: Writing a ‘1’ to the RxReset bit will reset the receive datapath, excluding the
MAC portions, including all (read-only) registers in the receive datapath, as well as the
RxConsumeIndex register in the host registers module. A soft reset of the receive
datapath will abort all AHB transactions of the receive datapath. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Rx datapath will clear
the RxStatus bit in the Status register.