NXP Semiconductors LPC24XX UM10237 - Manual (Page 224)

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User manual Rev. 04 — 26 August 2009 224 of 792
NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
7.1.6 Maximum Frame Register (MAXF - 0xFFE0 0014)
The Maximum Frame register (MAXF) has an address of 0xFFE0 0014. Its bit definition is
shown in
Table 11–193 .
7.1.7 PHY Support Register (SUPP - 0xFFE0 0018)
The PHY Support register (SUPP) has an address of 0xFFE0 0018. The SUPP register
provides additional control over the RMII interface. The bit definition of this register is
shown in
Table 11–194 .
Unused bits in the PHY support register should be left as zeroes.
7.1.8 Test Register (TEST - 0xFFE0 001C)
The Test register (TEST) has an address of 0xFFE0 001C. The bit definition of this
register is shown in
Table 11–195 . These bits are used for testing purposes only.
Table 192. Collision Window / Retry register (CLRT - address 0xFFE0 0010) bit description
Bit Symbol Function Reset
value
3:0 RETRANSMISSION
MAXIMUM This is a programmable field specifying the number of retransmission attempts
following a collision before aborting the packet due to excessive collisions. The
Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. 0xF
7:4 - Reserved. User software should not write ones to reserved bits. The value read from
a reserved bit is not defined. 0x0
13:8 COLLISION
WINDOW This is a programmable field representing the slot time or collision window during
which collisions occur in properly configured networks. The default value of 0x37
(55d) represents a 56 byte window following the preamble and SFD. 0x37
31:14 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined. NA
Table 193. Maximum Frame register (MAXF - address 0xFFE0 0014) bit description
Bit Symbol Function Reset
value
15:0 MAXIMUM FRAME
LENGTH This field resets to the value 0x0600, which represents a maximum receive frame of
1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged
frame adds four octets for a total of 1522 octets. If a shorter maximum length
restriction is desired, program this 16 bit field. 0x0600
31:16 - Unused 0x0
Table 194. PHY Support register (SUPP - address 0xFFE0 0018) bit description
Bit Symbol Function Reset
value
7:0 - Unused 0x0
8 SPEED This bit configures the Reduced MII logic for the current operating speed. When set,
100 Mbps mode is selected. When cleared, 10 Mbps mode is selected. 0
31:9 - Unused 0x0