NXP Semiconductors LPC24XX UM10237 - Manual (Page 313)

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User manual Rev. 04 — 26 August 2009 313 of 792
NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
The LCD_INTMSK register controls whether various LCD interrupts occur.Setting bits in
this register enables the corresponding raw interrupt LCD_INTRAW status bit values to be
passed to the LCD_INTSTAT register for processing as interrupts.
The contents of the LCD_INTMSK register are described in Table 12–268 .
4 LcdBW STN LCD monochrome/color selection.
0 = STN LCD is color.
1 = STN LCD is monochrome.
This bit has no meaning in TFT mode.
0x0
3:1 LcdBpp LCD bits per pixel:
Selects the number of bits per LCD pixel:
000 = 1 bpp.
001 = 2 bpp.
010 = 4 bpp.
011 = 8 bpp.
100 = 16 bpp.
101 = 24 bpp (TFT panel only).
110 = 16 bpp, 5:6:5 mode.
111 = 12 bpp, 4:4:4 mode.
0x0
0 LcdEn LCD enable control bit.
0 = LCD disabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are low.
1 = LCD enabled. Signals LCDLP, LCDDCLK, LCDFP,
LCDENAB, and LCDLE are high.
See LCD power-up and power-down sequence for details on
LCD power sequencing.
0x0
Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
Bits Function Description Reset
value
Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
Bits Function Description Reset
value
31:5 reserved Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
4 BERIM AHB master error interrupt enable.
0: The AHB Master error interrupt is disabled.
1: Interrupt will be generated when an AHB Master error occurs.
0x0
3 VCompIM Vertical compare interrupt enable.
0: The vertical compare time interrupt is disabled.
1: Interrupt will be generated when the vertical compare time (as
defined by LcdVComp field in the LCD_CTRL register) is
reached.
0x0