Section 17–4.14, Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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UM10237_4
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User manual
Rev. 04 — 26 August 2009
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NXP Semiconductors
UM10237
Chapter 17: LPC24XX UART1
4.13 UART1 Scratch Pad Register (U1SCR - 0xE001 001C)
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
4.14 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020)
The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
5
DSR
Data Set Ready State. Complement of input signal DSR. This bit is
connected to U1MCR[0] in modem loopback mode.
0
6
RI
Ring Indicator State. Complement of input RI. This bit is connected
to U1MCR[2] in modem loopback mode.
0
7
DCD
Data Carrier Detect State. Complement of input DCD. This bit is
connected to U1MCR[3] in modem loopback mode.
0
Table 409. UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description
Bit Symbol Value Description
Reset
Value
Table 410. UART1 Scratch Pad Register (U1SCR - address 0xE001 0014) bit description
Bit Symbol Description
Reset Value
7:0 Pad
A readable, writable byte.
0x00
Table 411. Auto-baud Control Register (U1ACR - address 0xE001 0020) bit description
Bit
Symbol
Value Description
Reset value
0
Start
This bit is automatically cleared after auto-baud
completion.
0
0
Auto-baud stop (auto-baud is not running).
1
Auto-baud start (auto-baud is running).Auto-baud run
bit. This bit is automatically cleared after auto-baud
completion.
1
Mode
Auto-baud mode select bit.
0
0
Mode 0.
1
Mode 1.
2
AutoRestart 0
No restart
0
1
Restart in case of time-out (counter restarts at next
UART1 Rx falling edge)
0
7:3
-
NA
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
0
8
ABEOIntClr
End of auto-baud interrupt clear bit (write only
accessible).
0
0
Writing a 0 has no impact.
1
Writing a 1 will clear the corresponding interrupt in the
U1IIR.