NXP Semiconductors LPC24XX UM10237 - Manual (Page 52)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 52 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
3.2.7 PLL Interrupt: PLOCK
The PLOCK bit in the PLLSTAT register reflects the lock status of the PLL. When the PLL
is enabled, or parameters are changed, the PLL requires some time to establish lock
under the new conditions. PLOCK can be monitored to determine when the PLL may be
connected for use. The value of PLOCK may not be stable when the PLL reference
frequency (F
REF
, the frequency of REFCLK, which is equal to the PLL input frequency
divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these
cases, the PLL may be assumed to be stable after a start-up time has passed. This time is
500
μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less
than 400 kHz
PLOCK is connected to the interrupt controller. This allows for software to turn on the PLL
and continue with other functions without having to wait for the PLL to achieve lock. When
the interrupt occurs, the PLL may be connected, and the interrupt disabled.
3.2.8 PLL Modes
The combinations of PLLE and PLLC are shown in Table 4–48 .
Table 47. PLL Status register (PLLSTAT - address 0xE01F C088) bit description
Bit Symbol Description Reset
value
14:0 MSEL Read-back for the PLL Multiplier value. This is the value currently
used by the PLL, and is one less than the actual multiplier. 0
15 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
23:16 NSEL Read-back for the PLL Pre-Divider value. This is the value currently
used by the PLL, and is one less than the actual divider. 0
24 PLLE Read-back for the PLL Enable bit. When one, the PLL is currently
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated. 0
25 PLLC Read-back for the PLL Connect bit. When PLLC and PLLE are both
one, the PLL is connected as the clock source for the LPC2400.
When either PLLC or PLLE is zero, the PLL is bypassed. This bit is
automatically cleared when Power-down mode is activated. 0
26 PLOCK Reflects the PLL Lock status. When zero, the PLL is not locked.
When one, the PLL is locked onto the requested frequency. See
text for details. 0
31:27 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
Table 48. PLL control bit combinations
PLLC PLLE PLL Function
0 0 PLL is turned off and disconnected. The PLL outputs the unmodified clock
input.
0 1 The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
1 0 Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
1 1 The PLL is active and has been connected as the system clock source.