NXP Semiconductors LPC24XX UM10237 - Manual (Page 745)

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User manual Rev. 04 — 26 August 2009 745 of 792
NXP Semiconductors
UM10237
Chapter 34: LPC24XX Embedded Trace Module (ETM)
[1] For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)".
4. Pin description
5. Register description
The ETM contains 29 registers as shown in Table 34–681 below. They are described in
detail in the ARM IHI 0014E document published by ARM Limited.
External Inputs 2
External Outputs 0
FIFOFULL Present Yes (Not wired)
FIFO depth 10 bytes
Trace Packet Width 4/8
Table 679. ETM configuration
Resource number/type Small [1]
Table 680. ETM pin description
Pin Name Type Description
TRACECLK Output Trace Clock. The trace clock signal provides the clock for the trace
port. PIPESTAT[2:0], TRACESYNC, and TRACEPKT[3:0] signals are
referenced to the rising edge of the trace clock. This clock is not
generated by the ETM block. It is to be derived from the system clock.
The clock should be balanced to provide sufficient hold time for the
trace data signals. Half rate clocking mode is supported. Trace data
signals should be shifted by a clock phase from TRACECLK. Refer to
Figure 3.14 page 3.26 and figure 3.15 page 3.27 in "ETM7 Technical
Reference Manual" (ARM DDI 0158B)
, for example circuits that
implements both half-rateclocking and shifting of the trace data with
respect to the clock. For TRACECLK timings refer to section 5.2 on
page 5-13 in "Embedded Trace Macrocell Specification" (ARM IHI
0014E)
.
PIPESTAT[2:0] Output Pipe Line status. The pipeline status signals provide a cycle-by-cycle
indication of what is happening in the execution stage of the processor
pipeline.
TRACESYNC Output Trace synchronization. The trace sync signal is used to indicate the
first packet of a group of trace packets and is asserted HIGH only for
the first packet of any branch address.
TRACEPKT[3:0] Output Trace Packet. The trace packet signals are used to output packaged
address and data information related to the pipeline status. All packets
are eight bits in length. A packet is output over two cycles. In the first
cycle, Packet[3:0] is output and in the second cycle, Packet[7:4] is
output.
EXTIN[0] Input External Trigger Input