NXP Semiconductors LPC24XX UM10237 - Manual (Page 652)

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User manual Rev. 04 — 26 August 2009 652 of 792
NXP Semiconductors
UM10237
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
6.2.5 Counter Increment Select Mask Register (CISS - 0xE002 4040)
The CISS register provides a way to obtain millisecond-range periodic CPU interrupts
from the Real Time Clock. This can allow freeing up one of the general purpose timers, or
support power saving by putting the CPU into a reduced power mode between periodic
interrupts.
Carry out signals from different stages of the Clock Tick Counter are used to generate the
sub-second interrupts. The possibilities range from 16 counts of the CTC (about
488 microseconds), up to 2,048 counts of the CTC (about 62.5 milliseconds). The
available counts and corresponding times are given in
Table 26–571 .
Table 570. Counter Increment Interrupt Register (CIIR - address 0xE002 400C) bit description
Bit Symbol Description Reset
value
0 IMSEC When 1, an increment of the Second value generates an interrupt. NA
1 IMMIN When 1, an increment of the Minute value generates an interrupt. NA
2 IMHOUR When 1, an increment of the Hour value generates an interrupt. NA
3 IMDOM When 1, an increment of the Day of Month value generates an
interrupt. NA
4 IMDOW When 1, an increment of the Day of Week value generates an interrupt. NA
5 IMDOY When 1, an increment of the Day of Year value generates an interrupt. NA
6 IMMON When 1, an increment of the Month value generates an interrupt. NA
7 IMYEAR When 1, an increment of the Year value generates an interrupt. NA
Table 571. Counter Increment Select Mask register (CISS - address 0xE002 4040) bit description
Bit Symbol Value Description Reset
value
2:0 SubSecSel SubSecSelSub-Second Select. This field selects a count for the sub-second interrupt as
follows: NC
000 An interrupt is generated on every 16 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 488 microseconds.
001 An interrupt is generated on every 32 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 977 microseconds.
010 An interrupt is generated on every 64 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 1.95 milliseconds.
011 An interrupt is generated on every 128 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 3.9 milliseconds.
100 An interrupt is generated on every 256 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 7.8 milliseconds.
101 An interrupt is generated on every 512 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 15.6 milliseconds.
110 An interrupt is generated on every 1024 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 31.25 milliseconds.
111 An interrupt is generated on every 2048 counts of the Clock Tick Counter. At 32.768 kHz,
this generates an interrupt approximately every 62.5 milliseconds.
6:3 Unused Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined. NA