Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
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NXP Semiconductors
UM10237
Chapter 12: LPC24XX LCD controller
7.13 Upper Panel Current Address register (LCD_UPCURR, RW - 0xFFE1
002C)
The LCD_UPCURR register is Read-Only, and contains an approximate value of the
upper panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
The contents of the LCD_UPCURR register are described in
.
7.14 Lower Panel Current Address register (LCD_LPCURR, RW - 0xFFE1
0030)
The LCD_LPCURR register is Read-Only, and contains an approximate value of the lower
panel data DMA address when read.
Note: This register can change at any time and therefore can only be used as a rough
indication of display position.
The contents of the LCD_LPCURR are described in
.
7.15 Color Palette registers (LCD_PAL, RW - 0xFFE1 0200 to 0xFFE1 03FC)
The LCD_PAL register contain 256 palette entries organized as 128 locations of two
entries per word.
2
LNBUIC
LCD next address base update interrupt clear.
Writing a 1 to this bit clears the LCD next address base update
interrupt.
0x0
1
FUFIC
FIFO underflow interrupt clear.
Writing a 1 to this bit clears the FIFO underflow interrupt.
0x0
0
reserved
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
-
Table 271. Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)
Bits
Function
Description
Reset
value
Table 272. Upper Panel Current Address register (LCD_UPCURR, RW - 0xFFE1 002C)
Bits
Function
Description
Reset
value
31:0
LCDUPCURR
LCD Upper Panel Current Address.
Contains the current LCD upper panel data DMA address.
0x0
Table 273. Lower Panel Current Address register (LCD_LPCURR, RW - 0xFFE1 0030)
Bits
Function
Description
Reset
value
31:0
LCDLPCURR
LCD Lower Panel Current Address.
Contains the current LCD lower panel data DMA address.
0x0