NXP Semiconductors LPC24XX UM10237 - Manual (Page 445)

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UM10
237_
4
©
NXP
B.V
. 2009.
Al
l r
ig
h
ts
r
e
s
e
rv
ed.
User m
a
nu
al
Rev
. 04 — 26
Aug
u
st
2009
445 of
792
N
X
P Semi
conductor
s
UM10237
C
h
apter 17: LPC24X
X UAR
T1
Table 396. UART1 register map
Name Description Bit functions and addresses Access Reset
Value [1]
Address
MSB LSB
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
U1RBR Receiver
Buffer
Register 8 bit Read Data RO NA 0xE001 0000
(DLAB=0)
U1THR Transmit
Holding
Register 8 bit Write Data WO NA 0xE001 0000
(DLAB=0)
U1DLL Divisor Latch
LSB 8 bit Data R/W 0x01 0xE001 0000
(DLAB=1)
U1DLM Divisor Latch
MSB 8 bit Data R/W 0x00 0xE001 0004
(DLAB=1)
U1IER Interrupt
Enable
Register Reserved Enable
Autobaud
Time-Out
Interrupt
Enable
End of
Autobaud
Interrupt
R/W 0x00 0xE001 0004
(DLAB=0)
Enable
CTS
Interrupt
0 Enable
Modem
Status
interrupt
Enable
RX Line
Status
Interrupt
Enable
THRE
Interrupt
Enable RX
Data
Available
Interrupt
U1IIR Interrupt ID
Register Reserved ABTO Itn ABEO int RO 0x01 0xE001 0008
FIFOs Enabled 0 IIR3 IIR2 IIR1 IIR0
U1FCR FIFO Control
Register RX Trigger Reserved TX FIFO
Reset
RX FIFO
Reset
FIFO
Enable
WO 0x00 0xE001 0008
U1LCR Line Control
Register DLAB Set Break Stick
Parity
Even
Parity
Select
Parity
Enable
Number
of Stop
Bits
Word Length Select R/W 0x00 0xE001 000C
U1MCR Modem
Control
Register CTSen RTSen 0 Loop
Back 0 RTS DTR R/W 0x00 0xE001 0010
U1LSR Line Status
Register RX FIFO
Error
TEMT THRE BI FE PE OE DR RO 0x60 0xE001 0014
U1MSR Modem Status
Register DCD RI DSR CTS Delta
DCD
Trailing
Edge RI
Delta DSR Delta CTS RO 0x00 0xE001 0018
U1SCR Scratch Pad
Register 8 bit Data R/W 0x00 0xE001 001C