NXP Semiconductors LPC24XX UM10237 - Manual (Page 24)

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User manual Rev. 04 — 26 August 2009 24 of 792
NXP Semiconductors
UM10237
Chapter 2: LPC24XX Memory mapping
Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 2–6 “Memory mapping
control” on page 24 .
6. Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. This allows code running in different memory spaces
to have control of the interrupts.
6.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, the microcontroller will fetch an instruction
residing on exception corresponding address as described in
Table 2–18 “ARM exception
vector locations” on page 22 . The MEMMAP register determines the source of data that
will fill this table.
6.2 Memory mapping control usage notes
Memory Mapping Control simply selects one out of three available sources of data (sets of
64 bytes each) necessary for handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, ARM core will always
fetch 32 bit data "residing" on 0x0000 0008 see
Table 2–18 “ARM exception vector
locations” on page 22 . This means that when MEMMAP[1:0] = 10 (User RAM Mode),
Table 20. Memory mapping control registers
Name Description Access Reset
value Address
MEMMAP Memory mapping control. Selects whether the
ARM interrupt vectors are read from the Boot
ROM, User Flash, or RAM.
R/W 0x00 0xE01F C040
Table 21. Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description
Bit Symbol Value Description Reset
value
1:0 MAP 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 00
01 User Flash Mode. Interrupt vectors are not re-mapped and reside
in Flash.
Remark: This mode is for parts with flash only. Value 01 is
reserved for flashless parts LPC2420/60/70.
10 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
11 User External Memory Mode. Interrupt vectors are re-mapped to
external memory bank 0.
Warning: Improper setting of this value may result in incorrect operation of
the device.
7:2 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA