NXP Semiconductors LPC24XX UM10237 - Manual (Page 86)

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User manual Rev. 04 — 26 August 2009 86 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC -
0xFFE0 804C)
The EMCDynamicTRFC register enables you to program the auto-refresh period, and
auto-refresh to active command period, tRFC. It is recommended that this register is
modified during system initialization, or when there are no current or outstanding
transactions. This can be ensured by waiting until the EMC is idle, and then entering
low-power, or disabled mode. This value is normally found in SDRAM data sheets as
tRFC, or sometimes as tRC. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–81 shows the bit assignments for the EMCDynamicTRFC register.
10.15 Dynamic Memory Exit Self-refresh register (EMCDynamictXSR -
0xFFE0 8050)
The EMCDynamicTXSR register enables you to program the exit self-refresh to active
command time, tXSR. It is recommended that this register is modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
This value is normally found in SDRAM data sheets as tXSR. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table 5–82 shows the bit assignments for the EMCDynamicTXSR register.
Table 80. Dynamic Mempry Active to Active Command Period register (EMCDynamictRC -
address 0xFFE0 8048) bit description
Bit Symbol Value Description Reset
Value
4:0 Active to active
command
period (tRC) 0x0 -
0x1E n + 1 clock cycles. The delay is in CCLK cycles. 0x1F
0xF 32 clock cycles (POR reset value).
31:5 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 81. Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - address
0xFFE0 804C) bit description
Bit Symbol Value Description Reset
Value
4:0 Auto-refresh
period and
auto-refresh to
active command
period (tRFC) 0x0 -
0x1E n + 1 clock cycles. The delay is in CCLK cycles. 0x1F
0xF 32 clock cycles (POR reset value).
31:5 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA