NXP Semiconductors LPC24XX UM10237 - Manual (Page 643)

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User manual Rev. 04 — 26 August 2009 643 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
6.5 PWM Capture Control Register (PWM0CCR - 0xE001 4028 and
PWM1CCR 0xE001 8028)
The Capture Control register is used to control whether any of the Capture registers is
loaded with the value in the Timer Counter when a capture event occurs on PCAP0[0] or
PCAP1[1:0], and whether an interrupt is generated by the capture event. Setting both the
rising and falling bits at the same time is a valid configuration, resulting in a capture event
for both edges. In the descriptions below, “n” represents the Timer number, 0 or 1.
Note: If Counter mode is selected for a particular PCAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other two PCAP inputs.
16 PWMMR5R 1 Reset on PWMMR5: the PWMTC will be reset if PWMMR5
matches it.
0
0 This feature is disabled.
17 PWMMR5S 1 Stop on PWMMR5: the PWMTC and PWMPC will be stopped
and PWMTCR[0] will be set to 0 if PWMMR5 matches the
PWMTC.
0
0 This feature is disabled
18 PWMMR6I 1 Interrupt on PWMMR6: an interrupt is generated when
PWMMR6 matches the value in the PWMTC.
0
0 This interrupt is disabled.
19 PWMMR6R 1 Reset on PWMMR6: the PWMTC will be reset if PWMMR6
matches it.
0
0 This feature is disabled.
20 PWMMR6S 1 Stop on PWMMR6: the PWMTC and PWMPC will be stopped
and PWMTCR[0] will be set to 0 if PWMMR6 matches the
PWMTC.
0
0 This feature is disabled
31:21 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR -
address 0xE000 8014) bit description
Bit Symbol Value Description Reset
Value
Table 562: PWM Capture Control Register (PWM0CCR - address 0xE001 4028 and PWM1CCR
address 0xE001 8028) bit description
Bit Symbol Value Description Reset
Value
0 Capture on
PCAPn.0
rising edge 0 This feature is disabled. 0
1 A synchronously sampled rising edge on the PCAPn.0 input
will cause CR0 to be loaded with the contents of the TC.
1 Capture on
PCAPn.0
falling edge 0 This feature is disabled. 0
1 A synchronously sampled falling edge on PCAPn.0 will cause
CR0 to be loaded with the contents of TC.
2 Interrupt on
PCAPn.0
event 0 This feature is disabled. 0
1 A CR0 load due to a PCAPn.0 event will generate an
interrupt.