NXP Semiconductors LPC24XX UM10237 - Manual (Page 723)

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User manual Rev. 04 — 26 August 2009 723 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.1.5 Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010)
The DMACIntErrClr Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is HIGH causes the corresponding bit in the
status register to be cleared. Data bits that are LOW have no effect on the corresponding
bit in the register.
Table 32–657 shows the bit assignments of the DMACIntErrClr Register.
6.1.6 Raw Interrupt Terminal Count Status Register (DMACRawIntTCStatus -
0xFFE0 4014)
The DMACRawIntTCStatus Register is read-only and indicates which DMA channel is
requesting a transfer complete (terminal count interrupt) prior to masking. A HIGH bit
indicates that the terminal count interrupt request is active prior to masking.
Table 32–658
shows the bit assignments of the DMACRawIntTCStatus Register.
6.1.7 Raw Error Interrupt Status Register (DMACRawIntErrorStatus -
0xFFE0 4018)
The DMACRawIntErrorStatus Register is read-only and indicates which DMA channel is
requesting an error interrupt prior to masking. A HIGH bit indicates that the error interrupt
request is active prior to masking.
Table 32–659 shows the bit assignments of register of
the DMACRawIntErrorStatus Register.
Table 656. Interrupt Error Status register (DMACIntErrorStatus - address 0xFFE0 400C) bit
description
Bit Symbol Description Reset
Value
0 IntErrorStatus0 Interrupt error status for channel 0. 0x0
1 IntErrorStatus1 Interrupt error status for channel 1. 0x0
31:2 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA
Table 657. Interrupt Error Clear register (DMACIntErrClr - address 0xFFE0 4010) bit
description
Bit Symbol Description Reset
Value
0 IntErrClr0 Writing a 1 clears the error interrupt request for channel 0
(IntErrorStatus0). -
1 IntErrClr1 Writing a 1 clears the error interrupt request for channel 1
(IntErrorStatus1). -
31:2 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA
Table 658. Raw Interrupt Terminal Count Status register (DMACRawIntTCStatus - address
0xFFE0 4014) bit description
Bit Symbol Description Reset
Value
0 RawIntTCStatus0 Status of the terminal count interrupt for channel 0 prior to
masking.
-
1 RawIntTCStatus1 Status of the terminal count interrupt for channel 1 prior to
masking.
-
31:2 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA