Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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UM10237_4
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User manual
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NXP Semiconductors
UM10237
Chapter 13: LPC24XX USB device controller
9.8.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xFFE0
C2B0)
Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntClr is a write only register.
9.8.15 USB New DD Request Interrupt Set register (USBNDDRIntSet - 0xFFE0
C2B4)
Writing one to a bit in this register sets the corresponding bit in the USBNDDRIntSt
register. Writing zero has no effect. USBNDDRIntSet is a write only register
9.8.16 USB System Error Interrupt Status register (USBSysErrIntSt - 0xFFE0 C2B8)
If a system error (AHB bus error) occurs when transferring the data or when fetching or
updating the DD the corresponding bit is set in this register. USBSysErrIntSt is a read only
register.
9.8.17 USB System Error Interrupt Clear register (USBSysErrIntClr - 0xFFE0 C2BC)
Writing one to a bit in this register clears the corresponding bit in the USBSysErrIntSt
register. Writing zero has no effect. USBSysErrIntClr is a write only register.
Table 342. USB New DD Request Interrupt Clear register (USBNDDRIntClr - address 0xFFE0
C2B0) bit description
Bit
Symbol
Value
Description
Reset value
31:0 EPxx
Clear endpoint xx (2
≤
xx
≤
31) new DD interrupt request. 0
0
No effect.
1
Clear the EPxx new DD interrupt request in the
USBNDDRIntSt register.
Table 343. USB New DD Request Interrupt Set register (USBNDDRIntSet - address 0xFFE0
C2B4) bit description
Bit
Symbol
Value
Description
Reset value
31:0
EPxx
Set endpoint xx (2
≤
xx
≤
31) new DD interrupt request.
0
0
No effect.
1
Set the EPxx new DD interrupt request in the
USBNDDRIntSt register.
Table 344. USB System Error Interrupt Status register (USBSysErrIntSt - address
0xFFE0 C2B8) bit description
Bit
Symbol
Value
Description
Reset
value
31:0
EPxx
Endpoint xx (2
≤
xx
≤
31) System Error Interrupt request.
0
0
There is no System Error Interrupt request for endpoint xx.
1
There is a System Error Interrupt request for endpoint xx.