NXP Semiconductors LPC24XX UM10237 - Manual (Page 53)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 53 of 792
NXP Semiconductors
UM10237
Chapter 4: LPC24XX Clocking and power control
3.2.9 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
3.2.10 PLL and Power-down mode
Power-down mode automatically turns off and disconnects the PLL. Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
3.2.11 PLL frequency calculation
The PLL equations use the following parameters:
The PLL output frequency (when the PLL is both active and connected) is given by:
F
CCO
= (2
× M × F
IN
) / N
The PLL inputs and settings must meet the following:
• F
IN
is in the range of 32 kHz to 50 MHz.
• F
CCO
is in the range of 275 MHz to 550 MHz.
The PLL equation can be solved for other PLL parameters:
Table 49. PLL Feed register (PLLFEED - address 0xE01F C08C) bit description
Bit Symbol Description Reset
value
7:0 PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect. 0x00
Table 50. PLL frequency parameter
Parameter Description
F
IN
the frequency of pllclkin from the Clock Source Selection Multiplexer.
F
CCO
the frequency of the pllclk (output of the PLL Current Controlled Oscillator)
N PLL Pre-divider value from the NSEL bits in the PLLCFG register (PLLCFG
NSEL field + 1). N is an integer from 1 through 32.
M PLL Multiplier value from the MSEL bits in the PLLCFG register (PLLCFG
MSEL field + 1). Not all potential values are supported. See below.
F
REF
PLL internal reference frequency, FIN divided by N.