NXP Semiconductors LPC24XX UM10237 - Manual (Page 175)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 175 of 792
NXP Semiconductors
UM10237
Chapter 8: LPC24XX Pin configuration
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I 2 C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I 2 C-bus is floating and does not disturb the I 2 C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[8] Pad provides special analog functionality.
[9] Pad provides special analog functionality.
[10] Pad provides special analog functionality.
[11] Pad provides special analog functionality.
[12] Pad provides special analog functionality.
[13] Pad provides special analog functionality.
[14] Pad provides special analog functionality.
[15] Either the I 2 S function or the LCD function is selectable.
[16] Either the USB OTG function or the LCD function is selectable.
[17] Either the trace function or the LCD function is selectable.
[18] Either one of the external interrupts EINT1 to EINT3 or the LCD function is selectable.
[19] Either one of the timer outputs MAT2[1] and MAT2[0] or the LCD function is selectable.
6. LPC2420/60/70 boot control
The flashless LPC2420, LPC2460, and LPC2470 use pins P3[15]/D15 and P3[14]/D14 for
configuring the external memory bus during the boot process. These pins are sampled
during Power-on Reset (POR). See
Table 8–125 for possible settings of the boot control
pins.
During the boot process, external memory banks 0 and 1 are configured with the same
data bus width determined by the setting of the two boot pins P3[15]/D15 and P3[14]/D14.
Unused address pins (A0 when booting from 16-bit wide external memory, A1 and A0
when booting from 32-bit wide memory) are configured as GPIO.
The boot loader remaps the vector table to external memory (see Table 2–21 , MEMAP =
0x3) and branches to address 0x0. The external boot memory must be connected to chip
select 1 (CS1). Note that CS1 is mirrored onto CS0 because the address mirror bit is set
Table 125. Boot control on pins P3[15]/D15 and P3/14]/D14
P3[15]/D15 P3[14]/D14 Description
BOOT1 BOOT0
0 0 Boot from 8-bit external memory on CS1. Sampled on POR signal.
0 1 Reserved. Do not use.
1 0 Boot from 32-bit external memory on CS1. Sampled on POR signal.
1 1 Boot from 16-bit external memory on CS1. Sampled on POR signal.