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5 a/d channel setting register (adsch, adech) – FUJITSU MB91460 SERIES FR60 User Manual

Page 910

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Chapter 44 A/D Converter

3.Registers of A/D Converter

Conversion time = CT value * CLKP cycle * 10 + (4 * CLKP)

Remarks : Do not set conversion time over 500 us.

[bit 9 to 0] ST9-0 (Analog input sampling time set)

These bits specify sampling time of analog input.
Initialized these bits to "0000101100" by reset.

Sampling time = ST value * CLKP cycle

Remarks : Do not set sampling time below 1.2 us when AVCC is below 4.5 V.

Necessary sampling time and ST value are calculated by following.
Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7
ST9 to ST0 = Tsamp / CLKP cycle

ST has to be set that sampling time is over Tsamp.
ex. CLKP = 32MHz, AVCC >= 4.5V, Rext = 200K
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [us]
ST = 15.17-6 / 31.25-9 = 485.44
ST has to be set over 486

D

(111100110

B

).

Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.

3.5 A/D Channel Setting Register (ADSCH, ADECH)

These registers specify the channels for the A/D converter to convert. Do not update these registers while the A/D
converting is operating.

A/D channel setting register (ADSCH, ADECH)

• ADSCH (ADC0): Address 01AAh (Access:

Word, Half-word, Byte

)

(See “

Meaning of Bit Attribute Symbols (Page No.10)

” for details of the attributes.)

15

14

13

12

11

10

9

8

Bit

-

-

-

ANS4

ANS3

ANS2

ANS1

ANS0

-

-

-

0

0

0

0

0

Initial

value

RX, W0

RX, W0

RX, W0

R/W

R/W

R/W

R/W

R/W

Attribute