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Data bus – FUJITSU MB91460 SERIES FR60 User Manual

Page 392

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Chapter 26 DMA Controller

5.Data Bus

5. Data Bus

This section shows the flow of data during 2-cycle transfer and fly-by transfer.

Flow of Data During 2-Cycle Transfer

Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer.

Figure 5-1 Examples of 2-Cycle Transfer (Continued on next page)

DMAC

D-bus

X-bus

I-bus

F-bus

D-bus

X-bus

I-bus

F-bus

D-bus

X-bus

I-bus

F-bus

D-bus

X-bus

I-bus

F-bus

D-bus

X-bus

I-bus

F-bus

D-bus

X-bus

I-bus

F-bus

RAM

CPU

MB91460

Read cycle

Read cycle

Read cycle

IO

Bus controller

DMAC

RAM

CPU

MB91460

Data buffer

Bus controller

Data buffer

Write cycle

Write cycle

Write cycle

IO

DMAC

RAM

CPU

MB91460

IO

DMAC

RAM

CPU

MB91460

IO

DMAC

RAM

CPU

MB91460

IO

DMAC

RAM

CPU

MB91460

IO

External area => external area transfer

External area => internal RAM area transfer

External area => built-in I/O area transfer

Bus controller

Data buffer

Bus controller

Data buffer

Bus controller

Data buffer

Bus controller

Data buffer

External bus I/F

External bus I/F

External bus I/F

External bus I/F

External bus I/F

External bus I/F