FUJITSU MB91460 SERIES FR60 - Manual (Page 682)

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Chapter 33 I2C Controller
1.Overview
■
Block Diagram
R-bus
I 2 C enable
Bus busy
Repeated start
Send/receive Bus Error
Start
Master
ACK enable
GC-ACK enable
General call
EN
CS4
ICCR
ICCR
CS3
CS2
CS1
CS0
Clock Divider 1
Sync
BB
IBSR
RSC
LRB
TRX
ADT
AL
Last Bit
Address Data
Arbitration Loss Detector
BER
IBCR
BEIE
INTE
INT
SCC
IBCR
MSS
ACK
GCAA
Interrupt Request
Start-Stop Condition
Generator
IDAR
Slave Address
Comparator
AAS
IBSR
Slave
SCL
Clock Divider 2 (by 12)
SCL Duty Cycle Generator
Clock Selector
ITBA ITMK
Shift Clock Generator
2 3 4 5 ... 32
ACK Generator
Bus Observer
ITMK
ENSB
enable 10 bit mode
R-Bus Clock (CLKP)
MCU
IRQ
ISBA ISMK
ISMK
enable 7 bit mode
ENTB
received ad. length
GCA
RAL
5 5
8
10
10
7
7
8
10
10 7
7
SDA
Noise
Filter
NSF
ICCR
enable
SCL
SDA