FUJITSU MB91460 SERIES FR60 - Manual (Page 735)

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Chapter 34 CAN Controller
2.Register Description
These registers hold the MsgVal bits of the 32 Message Objects. By reading out the MsgVal bits, the CPU
can check which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by
the CPU via the IFx Message Interface Registers.
If more than 32 message buffers are implemented then the following table gives an overview about the
additional flags:
Table 2-4 Additional flags when more than 32 message buffers exist
MsgVal32-1 Message Valid Bits (of all Message Objects)
0 This Message Object is ignored by the Message Handler.
1 This Message Object is configured and should be considered by the Message Handler.
addr+0 addr+1 addr+2 addr+3
MSGVAL 4 & 3 MsgVal 64-33 (address 0xB4) MsgVal64-57 MsgVal56-49 MsgVal48-41 MsgVal40-33
MSGVAL 6 & 5 MsgVal 96-65 (address 0xB8) MsgVal96-89 MsgVal88-81 MsgVal80-73 MsgVal72-65
MSGVAL 8 & 7 MsgVal 128-97 (address 0xBC) MsgVal128-121
MsgVal120-
113
MsgVal112-
105
MsgVal104-97