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FUJITSU MB91460 SERIES FR60 User Manual

Page 539

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Chapter 31 External Bus

2.External Bus Interface Registers

[Bits 7,6] W07-06 (Read -> Write Idle Cycle)

The read -> write idle cycle is set to prevent collision of read data and write data on the data bus when a write
cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals
maintain the high impedance state. If a write cycle follows a read cycle or an access operation to another chip
select area occurs after a read cycle, the specified idle cycle is inserted.

Table 2-7

"Settings of the Idle Cycle"

lists the settings for idle cycles.

[Bits 5, 4] W05, W04 (Write Recovery Cycle)

The write recovery cycle is set if a device that limits the access period after write access is to be controlled.
During a write recovery cycle, all chip select signals are negated and the data pins maintain the high
impedance state. If the write recovery cycle is set to 1 or more, a write recovery cycle is always inserted after
write access.

Table 2-8

"Settings for the Number of Write Recovery Cycles" lists the settings for the number of write

recovery cycles.

Table 2-7 Settings of the Idle Cycle

W07

W06

Read -> write idle cycles

0

0

0 cycle

0

1

1 cycle

1

0

2 cycles

1

1

3 cycles

Table 2-8 Settings for the Number of Write Recovery Cycles

W05

W04

Write recovery cycles

0

0

0 cycle

0

1

1 cycle

1

0

2 cycles

1

1

3 cycles