FUJITSU MB91460 SERIES FR60 - Manual (Page 211)

195
Chapter 13 Clock Control
4.Registers
4.3 DIV1R: Clock Division Setting Register 1
Sets the division ratio for the clocks used for internal device operation.
• DIVR1: Address 0487h (Access: Byte, Half-word)
(See “ Meaning of Bit Attribute Symbols (Page No.10) ” for details of the attributes.)
Sets the clock division ratio (relative to the base clock) for the clock used by the external bus interface (CLKT).
• Bit7-4: CLKT division selection
• Sets the clock division ratio for the clock used by the external bus interface (CLKT).
The 16 options listed in the table are available.
• Do not set a division ratio that exceeds the maximum operating frequency of the device.
• If you modify the CLKP division selection bits, the new division ratio applies from the next clock after the
setting is modified.
• Bit3-0: Reserved bit Always write “0” to this bit. The read value is the value written.
7 6 5 4 3 2 1 0 bit
T3 T2 T1 T0 – – – –
0 0 0 0 0 0 0 0 Initial value ( INIT pin input, watchdog reset )
X X X X X X X X Initial value (software reset)
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
T3-T0 External bus clock (CLKT) division ratio
0000
Φ/1 (initial value)
0001
Φ/2
0010
Φ/3
0011 Φ/4
0100
Φ/5
0101
Φ/6
0110
Φ/7
0111
Φ/8
1000
Φ/9
1001
Φ/10
1010 Φ/11
1011
Φ/12
1100
Φ/13
1101
Φ/14
1110
Φ/15
1111
Φ/16