FUJITSU MB91460 SERIES FR60 - Manual (Page 319)

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Chapter 23 Sub Oscillation Stabilisation Timer
5.Operation
5. Operation
5.1 Subclock Oscillation Stability Wait Interrupt
Figure 5-1 Reference
(1) Selects the interval (WS[1:0]) (In this example, 2
10
/F
CL-SUB
is selected.)
(2) Sets the timer so that it is cleared (WCL=“0”) by software.
(3) Sets the flag clear (WIF=“0”) and the interrupt request enable (WIE=“1”) by software.
(4) Sets the subclock stop release (OSCCR.OSCDS1=“0”) while the subclock is in operation by software.
(5) The subclock oscillation starts.
(6) Counts up with the subclock (source oscillation).
(7) Make the subclock oscillation stable.
(8) Makes the interval time be the selected time. (Detects the falling of 2 10 dividing.)
(9) If the flag (WIF) becomes “1”, the subclock oscillation stability wait interrupt request is generated.
(10) Processing cause by an interrupt (Software): Switching the operation clock (Sub-RUN => main RUN)
(11) Interrupt request disable (WIE=“0”) and the interrupt request clear (WIF=“0”).
Subclock stop bit
WIF
Clock timer
counting
Time
0400h
0000h
Main clock
(4)
(6)
(8)
Subclock
oscillation example
WCL
(1)
WIE
Subclock
(2)
(5)
(11)
(11)
Operation clock mode
(3)
(3)
(10)
(7)
(9)
(Bit 9) (8) 2 10