FUJITSU MB91460 SERIES FR60 - Manual (Page 681)

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Chapter 33 I2C Controller
1.Overview
Chapter 33 I
2
C Controller
1. Overview
The I
2
C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I
2
C
bus.
■
Features
• Master/slave transmitting and receiving functions
• Arbitration function
• Clock synchronization function
• General call addressing support
• Transfer direction detection function
• Repeated start condition generation and detection function
• Bus error detection function
• 7 bit addressing as master and slave
• 10 bit addressing as master and slave
• Possibility to give the interface a seven and a ten bit slave address
• Acknowledging upon slave address reception can be disabled (Master-only operation)
• Address masking to give interface several slave addresses (in 7 and 10 bit mode)
• Up to 400 kBit transfer rate
• Possibility to use built-in noise filters for SDA and SCL
• Can receive data at 400 kBit if R-Bus-Clock is higher than 6 MHz regardless of prescaler setting
• Can generate MCU interrupts on transmission and bus error events
• Supports being slowed down by a slave on bit and byte level
The I
2
C interface does not support SCL clock stretching on bit level since it can receive the full 400 kBit
datarate if the R-Bus-Clock (CLKP) is higher than 6 MHz regardless of the prescaler setting. However, clock
stretching on byte level is performed since SCL is pulled low during an interrupt (INT=‘1’ in IBCR2 register).