FUJITSU MB91460 SERIES FR60 - Manual (Page 32)

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Chapter 2 MB91460 Rev.A/Rev.B Overview
2.Features
• LIN-USART (LIN=Local Interconnect Network) : 16 channels
• Full-duplex double buffer system (4 ch with 16 byte RX/TX FIFO buffer each)
• With parity/without parity selectable
• 1 or 2 stop bits selectable
• 7 or 8 bits data length selectable
• NRZ type transfer format
• Asynchronous /synchronous communications selectable
• Master-slave communication function (multiprocessor mode)
• Dedicated baud rate prescaler is embedded in each channel
• External clock is able to use as transfer clock
• Parity error, frame error, and overrun error detecting functions
• SPI compatible
• LIN master and slave
• LIN USART 0/8 and ICU 0 co-operate (for LIN sync field in slave mode)
• LIN USART 1/9 and ICU 1 co-operate (for LIN sync field in slave mode)
• LIN USART 2/10 and ICU 2 co-operate (for LIN sync field in slave mode)
• LIN USART 3/11 and ICU 3 co-operate (for LIN sync field in slave mode)
• LIN USART 4/12 and ICU 4 co-operate (for LIN sync field in slave mode)
• LIN USART 5/13 and ICU 5 co-operate (for LIN sync field in slave mode)
• LIN USART 6/14 and ICU 6 co-operate (for LIN sync field in slave mode)
• LIN USART 7/15 and ICU 7 co-operate (for LIN sync field in slave mode)
• CAN : 6 channels
• Supports CAN protocol version 2.0 part A and B
• Bit rates up to 1 Mbit/s
• Up to 128 message objects
• Each message object has its own identifier mask
• Programmable FIFO mode (cocatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• I
2
C (400k fast mode) : 4 channels
• Master or slave transmission
• Arbitration function
• Clock synchronization function
• Slave address and general call address detect function
• Transfer direction detect function
• Start condition repeat generation and detection function
• Bus error detect function
• Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit addressing)
• Includes clock divider functionality
• SCL and SDA lines include optional noise filter. The noise filter allows the suppression of spikes in