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8 2-cycle transfer (i/o -> sdram/fcram) – FUJITSU MB91460 SERIES FR60 User Manual

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Chapter 31 External Bus

10.DMA Access Operation

2-Cycle Transfer (I/O -> External)

Figure 10-10

"Timing Chart for 2-Cycle Transfer (I/O -> External)" shows the operation timing chart for (TYP3-

0=0000

B

, AWR=0008

H

, IOWR=00

H

).

Figure 10-10

"Timing Chart for 2-Cycle Transfer (I/O -> External)" shows a case in which a wait is not set for

memory and I/O.

Figure 10-10 Timing Chart for 2-Cycle Transfer (I/O -> External)

The bus is accessed in the same way as an interface when the DMAC transfer is not performed.

In basic mode, DACKn/DEOPn is output both in the transfer source bus access and transfer destination bus
access.

10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM)

This section describes the operation of two - cycle transfer (I/O device to SDRAM/FCRAM).

memory address

I/O address

idle

DACKn

DEOPn

DACKn

DEOPn

DREQn

MCLK

AS

CSn

CSn

A[31:0]

D[31:0]

WRn

RD

FR30
compatible
mode

Basic
mode