beautypg.com

Edsu status register (bstat) – FUJITSU MB91460 SERIES FR60 User Manual

Page 430

background image

414

Chapter 29 MPU / EDSU

4.Registers

EDSU Status Register (BSTAT)

BIT[15:11]: IDX[4:0] - Channel Index Indication of MPUPV Trigger

In the case of triggering a memory protection violation (MPUPV), the index of the channel pair 0...15 is saved in The
IDX register, which caused the trigger. The channel pairs are normally used as range comparators.

If no MPU chanel has detected a hit on its address range, the default permissions apply. If the default permissions
are violated, IDX is set to the value 16 (overrun). If the permissions of a matching MPU channel are violated, IDX
shows the index of the appropriate break detection bits BIRQ_BD[31:0]. The break detection bits belonging tho this
comparator are BD[2*IDX] and BD[2*IDX+1].

In case of multiple range hits and/or trigger conditions, the channel with the highest priority trigger condittion is in-
dicated by IDX[4:0]. The priority raises with the channel index.

The channel index indication register can be read only.

Access Type Capture Register

In case of a trap caused by a memory protection violation or an operand/data value break condition, the status bits
[12:8] capture type information about the break causing operand access. In case of a memory protection fault due
to the violation of execution permissions, this information is also captured, regardless if there was an active operand
access or not.

Access type capture register are read only.

BIT[10]: CDMA - Capture DMA Indication

IDX

Description

0-15

Points to the channel number of the last protection violation

16

The last protection violation was caused by the violation of the default permissions

0

The operand access was executed by the CPU

1

The operand access was executed by the DMA controller

IDX4

IDX3

IDX2

IDX1

IDX0

CDMA

CSZ1

CSZ0

Bit no.

Read/write

(R)

(R)

(R)

(R)

(R)

(R)

(R)

(R)

Default value

(0)

(0)

(0)

(0)

(0)

(0)

(0)

(0)

EDSU Status Register byte 2

Address : F006

H

15

14

13

12

11

10

9

8

CRW1

CRW0

PV

RST

INT1

INT0

INTT

INTR

Bit no.

Read/write

(R)

(R)

(R/W) (R/W) (R/W) (R/W)

(R)

(R)

Default value

(0)

(0)

(0)

(1)

(0)

(0)

(0)

(0)

Address : F007

H

7

6

5

4

3

2

1

0

EDSU Status Register byte 3