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6 2-cycle transfer (external -> i/o) – FUJITSU MB91460 SERIES FR60 User Manual

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Chapter 31 External Bus

10.DMA Access Operation

10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)

This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation.

The timing is the same as for external I/O, RAM -> internal RAM.

2-Cycle Transfer (Internal RAM -> External I/O, RAM)

Figure 10-8

"Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)" shows the operation timing

chart for (TYP3-0=0000

B

, AWR=0008

H

, IOWR=00

H

).

Figure 10-8

"Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)" shows a case in which a wait

is not set on the I/O side.

Figure 10-8 Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)

The bus is accessed in the same way as an interface when DMAC transfer is not performed.

DACKn/DEOPn is not output in the internal RAM access cycles.

10.6 2-Cycle Transfer (External -> I/O)

This section explains 2-cycle transfer (external -> I/O) operation.

I/O address

DACKn

DEOPn

DACKn

DEOPn

DREQn

MCLK

AS

CSn

A[31:0]

D[31:0]

WRn

FR30
compatible
mode

Basic
mode

(I/O side)