Registers, 1 elvr: interrupt request level register – FUJITSU MB91460 SERIES FR60 User Manual
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Chapter 25 External Interrupt
4.Registers
4. Registers
4.1 ELVR: Interrupt Request Level Register
The register that selects request detection of external interrupts.
• ELVR0 (INT0-INT7): Address 032H (access: Half-word, Word)
(About attributes, see “
Meaning of Bit Attribute Symbols (Page No.10)
”.)
• ELVR1 (INT8-INT15): Address 036H (access: Half-word, Word)
(About attributes, see “
Meaning of Bit Attribute Symbols (Page No.10)
”.)
Interrupt request level bits (LBn, LAn) are registers that select request detection.
2 bits (LBn, LAn) are assigned to each external interrupt INTn.
When the request input is a level (LAn, LBn = “00” or “01”), and when the INTn pin input is the valid level, the
corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”.
Note: n = 0 to 15
15
14
13
12
11
10
9
8
Bit
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
Bit
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
15
14
13
12
11
10
9
8
Bit
LB15
LA15
LB14
LA14
LB13
LA13
LB12
LA12
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
Bit
LB11
LA11
LB10
LA10
LB9
LA9
LB8
LA8
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
LBn
LAn
Description
0
0
Detect “L” level and generate an interrupt request.
0
1
Detect “H” level and generate an interrupt request.
1
0
Detect the rise and generate an interrupt request.
1
1
Detect the fall and generate an interrupt request.