FUJITSU MB91460 SERIES FR60 - Manual (Page 593)

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Chapter 31 External Bus
7.Address/data Multiplex Interface
• As with the normal interface, auto-wait (AWR15-12), read -> write idle cycle (AWR7-6), write recovery (AWR5-
4), address -> CSn delay (AWR2), CSn -> RD/WRn setup delay (AWR1), and RD/WRn -> CSn hold delay
(AWR0) can be set.
• In areas for which the address/data multiplex interface is set, set 1(DBW1-0=00
B
) as the burst length.
■
With External Wait
Figure 7-2 "Timing Chart for the Address/Data Multiplex Interface (with External Wait)" shows the operation timing
chart for (TYP3-0=0101
B
, AWR=1008
H
).
Figure 7-2 Timing Chart for the Address/Data Multiplex Interface (with External Wait)
Making a setting such as TYP3-0=01x1
B
in the ACR register enables RDY input in the address/data multiplex
interface.
■
CSn -> RD/WRn Setup
Figure 7-3 "Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn Setup)" shows the operation
timing chart for (TYP3-0=0101
B
, AWR=100B
H
).
address[31:0]
address[15:0] data[15:0]
address[15:0] data[15:0]
External wait
Release
MCLK
AS
CSn
RD
A[31:0]
D[31:16]
D[31:16]
WR
RDY
WRITE
READ