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Caution – FUJITSU MB91460 SERIES FR60 User Manual

Page 168

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152

Chapter 9 Reset

10.Caution

10. Caution

• INIT pin input

Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also,
after turning on the power, ensure a sufficient oscillation stabilization wait time is provided for the
oscillation circuit by holding the input to the pin at the “L” level for the required time.

Note: The INIT reset triggered by INIT pin input initializes the oscillation stabilization wait time to its

minimum value.

• Watchdog reset

When a settings initialization reset (INIT) is triggered by a watchdog reset request, the oscillation
stabilization time is not initialized. Also, in main RUN or sub RUN mode, no oscillation stabilization wait
occurs in response to a watchdog reset request if the main clock is not halted.

• Software reset

If “1” (synchronous reset mode) is set to the synchronous reset operation enable bit (TBCR.SYNCR) when
an operation reset (RST) is triggered by a software reset request, the operation reset (RST) does not occur
until all bus access halts. Accordingly, there may be a long delay before the operation reset (RST) occurs,
depending on the bus usage.

• Settings initialization reset (INIT)

A settings initialization reset (INIT) invokes an operation reset (RST) after the oscillation stabilization wait
time elapses.

• Reset cause flags (INIT), (HSTB), (WDOG), (ERST), (SRST) and (LINIT)

• Reading the reset cause register clears all the reset cause flags to “0”.

• If more than one reset occurs before the reset cause register is read, the flag values are

ORed and more than one flag may be set to “1”.

• Reset mode

A settings initialization reset (INIT) initializes the reset mode to normal reset mode.

• DMA controller

As the DMA controller halts any transfer when a request is received, it does not cause any delay in
changing device state.

• Pin states during a reset

See “

8. Pin State Table (Page No.96)

” for details about pin states during a reset.