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Chapter 4 cpu architecture, Overview, Chapter 4 – FUJITSU MB91460 SERIES FR60 User Manual

Page 121: Cpu architecture

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Chapter 4 CPU Architecture

1.Overview

Chapter 4

CPU Architecture

This chapter describes the architecture of FR60 family CPU.

1. Overview

The CPUs of the FR60 family series employ RISC architecture and advanced function instructions for
embedded application.

CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. “32-
bit/16-bit bus converter” realizes the interface between CPU and peripheral functions. “Harvard/Princeton bus
converter” connects both of I-bus and D-bus and realizes the interface between CPU and bus controller.

Figure 1-1 Connection Diagram of Internal Architecture

FR CPU

Harvard/Princeton

Bus Converter

Embedded

I-Cache

Embedded

RAM

Embedded

Flash or

ROM

Embedded

RAM

Bus Converter

16 bit

32 bit

Bus Converter

32 <-> 16

DMA

Controller

External Bus

32

32

32

32

32

32

32

32

16

13

32

32

32

I-Bus

F-Bus

D-Bus

M-Bus

R-Bus

X-Bus

T-Bus

32

32

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