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7 mdh, mdl: multiply & divide register – FUJITSU MB91460 SERIES FR60 User Manual

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Chapter 5 CPU Registers

2.Dedicated Registers

2.7 MDH, MDL: Multiply & Divide Register

Multiply & Divide register (MDH/MDL) consists of 32 bits.

Figure 2-12 Bit Structure of Multiply & Divide Register (MDH/MDL)

This is the register for multiplication and division and consists of 32 bits.

Initial value by reset is indeterminate.

At the executing multiplication

When 32 bits x 32 bits multiplication, operation results of 64 bits are stored in multiplication/division store register as
the following allocation.

• MDH: Upper 32 bits

• MDL: Lower 32 bits

When 16 bits x 16 bits multiplication, results are stored as follows.

• MDH: Indeterminate.

• MDL: Results of 32 bits

At the executing division

Upon starting operation, dividend is stored in MDL.

By computing division by executing DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, results are stored in MDL
and MDH.

• MDH: Remainder

• MDL: Quotient

31 0

MDH

MDL