FUJITSU MB91460 SERIES FR60 - Manual (Page 578)

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Chapter 31 External Bus
5.Operation of the Ordinary bus interface
5. Operation of the Ordinary bus interface
This section explains operation of the ordinary bus interface.
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Ordinary Bus Interface
For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access and write access.
The following operational phases of the ordinary bus interface are explained below with the use of a timing chart.
• Basic timing (for successive accesses)
• WRn + byte control type
• Read -> write
• Write -> write
• Auto-wait cycle
• External wait cycle
• Synchronous write enable output
• CSn delay setting
• CSn -> RD/WRn setup, RD/WE -> CSn hold setting
• DMA fly-by transfer (I/O -> memory)
• DMA fly-by transfer (memory -> I/O)
5.1 Basic Timing
This section shows the basic timing for successive accesses.
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Basic Timing (For Successive Accesses)
Figure 5-1 "Basic Timing (For Successive Accesses)" shows the operation timing for (TYP3-0 = 0000
B
, AWR =
0008
H
)