FUJITSU MB91460 SERIES FR60 - Manual (Page 761)

745
Chapter 35 Free-Run Timer
8.Caution
8. Caution
• Clearing the free-run timer
• When you reset (the INIT pin input, the watchdog reset, the software reset), the counter is initialized to
“0000” and the counting is stopped.
• When the free-run timer is cleared by software, the counter is cleared and the clear request is generated
almost at the same time. If the counter is cleared by the compare-match, it is cleared when it is counted
up.
• After writing “1” in the clear bit (CLR), this request (CLR=“1”) is cleared at the same clear timing of the
free-run timer. When the clear operation of this CLR and writing “1” to the clear bit occurs at the same
time, the clear bit (CLR) keeps “1”, and after the next time the timer is cleared, it is cleared. (As a result,
the free-run timer is cleared twice.)
• The counter clear operation (the software, the overflow, and the compare-match) of the free-run timer is
enabled while the free-run timer is counting. To clear while the free-run timer is stopped, write 0000
H
in
the timer count data register.
• Write to the timer data register
When writing the value in the free-run timer, make sure to do so while the free-run timer is stopped
(STOP=“0”), and with word access.
• External clock operation
• The pulse width required for the external clock is 2/F
CLKP
minimum.
• When using an external clock, the timing of the compare-match output and the interrupt occurrence is the
same as the next count clock timing after the compare-match. Therefore, to allow the compare-match
output and interrupt generation, an external clock input of at least 1 clock is required after the compare-
match.
• Read/modify/write
The interrupt request flag (IVF) is always read “1” in read/modify/write.
• Interrupt request flag
If the interrupt request flag set timing and clear timing are simultaneous, the flag setting operation overrides
the flag clearing operation.