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FUJITSU MB91460 SERIES FR60 User Manual

Page 193

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177

Chapter 11 Memory Controller

8.Explanations of Registers

FLASH access cycle waveform

Figure

8-1

shows the example of a FLASH access cycle. In the FMWT register the three parts of the FLASH timing

tATD, tALEH, tEQ and tWTC can be configured independently. The table below lists the configuration values for
this example.

The resulting FLASH access cycle (tRC) time is 7 cycles (WTC+1).

• BIT[2:0]: PS[2:0] - Page size definition for Page Mode FLASH

PS is set to 0 after reset. Page Mode FLASH is disabled by default.

This setting defines the page size to 2^PS in number of bytes.

E.g. for Am29PL320D/MBM29PL3200 with a page size of 16 byte the value of PS has to be set to 4.

(Embedded FLASH memories on MB91460 series do not support page mode)

Symbol

Length

Setup

tATD

1.5 cycles

ATD=2

tALEH

1.5 cycles

ALEH=2

tEQ

3 cycles

EQ=5

tWTC

6 cycles

WTC=6

flash_start

FMA

ATDIN

EQIN

flash_wait

DO

tRC

tWTC

tATD

tEQ

tALEH

Figure 8-1 Timing of a FLASH access cycle