FUJITSU MB91460 SERIES FR60 - Manual (Page 203)

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Chapter 12 Instruction Cache
5.Settings for handling the I-Cache
To disable the I-Cache, set the ENAB bit to 0.
Idi #0x000003e7,r0 // I-Cache control register address
Idi #0B00000000,r1 // ENAB bit (bit 0)
stb r1,@r0 // Writing to register
In the resultant state (same as state prevailing after reset), there appears to be no cache.
The cache can be turned off if the processing may experience problems due to cache
overhead
4) Locking all cached instructions
To lock all the currently-cached instructions in the I-Cache, set the register GBLK bit to 1.
The ENAB bit must also be set to 1. If it is not, the cache is turned OFF, so instructions
locked in the cache cannot be used.
Idi #0x000003e7,r0 // I-Cache control register address
Idi #0B00100001,r1 // ENAB bit (bit 0)
// GBLK bit (bit 5)
stb r1,@r0 // Writing to register
5) Locking specific cached instructions
To lock a specific group of instructions (e.g., subroutines) in the cache, set the EOLK bit to 1
before executing such instructions.
Instructions locked in this manner are accessed rapidly as if using high-speed internal ROM.
Idi #0x000003e7,r0 // I-Cache control register address
Idi #0B00001001,r1 // ENAB bit (bit 0)
// EOLK bit (bit 3)
stb r1,@r0 // Writing to register
The above instruction lock becomes effective starting with the instruction next to the stb
instruction although it depends on the memory wait count. Set the EOLK bit to 0 when the
group of instructions which want to lock is ended.
Idi #0x000003e7,r0 // I-Cache control register address
Idi #0B00000101,r1 // ENAB bit (bit 0)
// EOLK bit (bit 3)
stb r1,@r0 // Writing to register
6) Unlocking cached instructions
To release the lock, proceed as follows.
Idi #0x000003e7,r0 // I-Cache control register address
Idi #0B00000000,r1 //Cash disabled
stb r1,@r0 // Writing to register
Idi #0B00000100,r1 // ELKR bit (bit 2)
stb r1,@r0 // Writing to register