FUJITSU MB91460 SERIES FR60 - Manual (Page 300)

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Chapter 21 Hardware Watchdog Timer
2.Configuration
2. Configuration
Hardware watchdog timer consists of two sub-blocks:
• Watchdog timer
• Timer control and status register
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Block diagram of the hardware watchdog timer
Figure 2-1 Block Diagram of hardware watchdog timer
Watchdog timer
This is a timer to supervise CPU operation. The counter needs to be cleared periodically after releasing the
reset.
Hardware watchdog timer control status register
This register has the reset flag and clear bit for the counter.
Occuring of the watchdog reset
If the counter has not been cleared periodically, this module provides a setting initialization reset (INIT). The
width of internal reset signal is 63 times the system base clock. After the watchdog reset the normal system
reset procedure starts. For more details about this procedure, see the corresponding section in the device
state description.