For fly-by (read/write) transfer, For burst, step, block, and demand transfers – FUJITSU MB91460 SERIES FR60 User Manual
Page 386
370
Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
Figure 3-7 Negate timing example of the DREQ pin input for 2-cycle external transfer --> internal transfer
•
If the transfer is internal <--> external: Negate before the last sense timing of the clock in the L section of the
external WRn pin output when accessing the transfer source for the last DMA transfer (Section of DACK =
1and WRn = L). If DREQ is negated later than this, a DMA request may be sensed, resulting in negation until
the next transfer.
●
For fly-by (read/write) transfer
For a demand transfer, be sure to set an address in an external area for the transfer destination.
•
For fly-by (read) transfer: After the IOWR pin output for the last DMA transfer goes to the H level, negate
DREQ while the external RD pin output is at the L level. (section where DACK=L & RD=L). If DREQ is negated
later than this, the negation may continue until the next transfer.
•
For fly-by (write) transfer: After the external WRn pin output for the last DMA transfer goes to the H level,
negate DREQ while IORD is at the L level. (section where DACK=L & RD=L). If DREQ is negated later than
this, the negation may continue until the next transfer.
Figure 3-8 Negate timing example of the DREQ pin input for fly-by (write) transfer
■
Timing of the DREQ Pin Input for Continuing Transfer over the Same Channel
●
For burst, step, block, and demand transfers
Operation in which transfer is continued over the same channel by the DREQ pin input cannot be guaranteed. If
DREQ is reasserted at the fastest timing to clear requests retained internally after the transfer ends, at least one
system clock cycle (one CLK output cycle) is provided to detect transfer requests for other channels. If, as a
result, a transfer request for another channel with a higher priority is detected, transfer on that channel will be
started.
DREQ (H level)
Area
Bus operation
CPU
SA
DA
SA
DA
SA
DA
SA
DA
CPU
DACK
DEOP
RD
WR
External D bus
*1
*1: External
*2: Internal
*2
*1
*2
*1
*2
*1
*2
DREQ (H level)
Area
DACK
DEOP
RD
WR
External D bus
Bus operation
*1
*2
*1
*2
*1
*2
*1
*2
*1: External
*2: Internal