FUJITSU MB91460 SERIES FR60 - Manual (Page 434)

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Chapter 29 MPU / EDSU
4.Registers
• operand address break,
• data value break,
• combined operand address and data value break and
• memory protection violation.
Writing ’0’ resets the BD[31:0] bits to ’0’. Writing ’1’ to these bits is ignored. On a Read Modify Write instruction all
BD bits are read as ’1’.
BD1/BD0 setting at enabled address range function (also valid for the other pairs of BD bits in neighbourhood):
If the operand address range function is enabled with ER0 in addition to the point enables EP1 and EP0, then the
BD1 and BD0 detection bits are set in the following manner:
Table 4-2 BD Coding for Match on Start/Endoint or Range
BD1 BD0 Compare value: Instruction, Operand Address, Data Value
0 0 No match (Default)
0 1 Match on point (compare value == BAD0)
1 0 Match on point (compare value == BAD1)
1 1 Match on range (BAD0 < compare value < BAD1)